HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 423

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
In transmitting serial data, the SCI operates as follows:
1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0, the SCI recognizes
2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new
Figure 13.6 shows an example of SCI transmit operation in the asynchronous mode.
that the transmit data register (TDR) contains new data, and loads this data from the TDR into
the transmit shift register (TSR).
transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCR, the
SCI requests a transmit-data-empty interrupt (TxI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
a. Start bit: one 0 bit is output.
b. Transmit data: seven or eight bits of data are output, LSB first.
c. Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit
d. Stop bit: one or two 1 bits (stop bits) are output.
e. Marking: output of 1 bits continues until the start bit of the next transmit data.
data from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SSR, outputs the stop bit, then
continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCR
is set to 1, a transmit-end interrupt (TEI) is requested.
is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also
be selected.
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 06, 2006 page 401 of 818
REJ09B0273-0500

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