HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 255

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Bits 2 to 0—I/O Control 3A2 to 3A0, 3C2 to 3C0, 4A2 to 4A0, 4C2 to 4C0, 5A2 to 5A0
(IO3A2 to IO3A0, IO3C2 to IO3C0, IO4A2 to IO4A0, IO4C2 to IO4C0, IO5A2 to IO5A0):
These bits select the general register (GR) function.
10.2.6
The trigger selection register (TGSR) is an 8-bit register. The ATU has one TGSR register.
TGSR is an 8-bit readable/writable register that selects an input pin (TIOA, TIOD) or the
compare-match output signal (TGR1A) from the channel 1 general register (GR1A) as the channel
0 input capture register (ICR0A, ICR0D) input trigger.
TGSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2:
IOxx2
0
1
Initial value:
Trigger Selection Register (TGSR)
Bit 1:
IOxx1
0
1
0
1
R/W:
Bit:
Bit 0:
IOxx0
0
1
0
1
0
1
0
1
R
7
0
Description
GR is an output
compare register
GR is input capture
register
R
6
0
R
5
0
R
4
0
0 output regardless of compare-match
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge
Input capture in GR on falling edge
Input capture in GR on both rising and
falling edges
Rev. 5.00 Jan 06, 2006 page 233 of 818
Section 10 Advanced Timer Unit (ATU)
R
3
0
TRG0D
R/W
2
0
REJ09B0273-0500
R
1
0
(Initial value)
TRG0A
R/W
0
0

Related parts for HD64F7051SFJ20V