HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 226

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 Advanced Timer Unit (ATU)
Block Diagram of Channels 3 and 4: Figure 10.5 shows a block diagram of ATU channels 3 and
4.
Rev. 5.00 Jan 06, 2006 page 204 of 818
REJ09B0273-0500
Legend:
TSTR: Timer start register (16 bits)
TMDR: Timer mode register (8 bits)
TCR:
TIOR:
TSRD: Timer status register D (8 bits)
TIERD: Timer interrupt enable register D (8 bits)
TCNT: Free-running counter (16 bits)
GR:
Interrupts:
OVI: Overflow interrupt
IMI: Input capture/compare-match interrupt
Note: * TMDR is used by channels 3 to 5.
1
0
TCLKA
TCLKB
/(m·2
TSTR
m
n
n
)
5
32
Timer control register (8 bits)
Timer I/O control register (8 bits)
General register (16 bits)
TSRDH and TIERDH are used by channel 3.
TSRDL and TIERDL are used by channels 4 and 5.
Figure 10.5 Block Diagram of Channels 3 and 4
Clock selection
Module data bus
Control logic
Comparator
OVI3/4
IMI3A/4A
IMI3B/4B
IMI3C/4C
IMI3D/4D
TIOA3/4
TIOB3/4
TIOC3/4
TIOD3/4

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