HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 310

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Advanced Timer Unit (ATU)
10.3.4
In ATU channels 0 to 5, when input capture is specified for the timer I/O control register (TIOR),
an input capture trigger signal is input from the corresponding external pin (TIA0 to TID0, TIOA1
to TIOF1, TIOA2, TIOB2, TIOA3 to TIOD3, TIO4A to TIOD4, TIOA5, TIOB5). A free-running
counter (TCNT) starts counting up when 1 is set in the timer start register (TSTR). When a trigger
signal is input from one of the above external pins, the counter value is transferred to the
corresponding register (ICR0AH/L to ICR0DH/L, OSBR, GR1A to GR1F, GR2A, GR2B, GR3A
to GR3D, GR4A to GR4D, GR5A, GR5B).
The detected edge of the external trigger input data can be selected by making a setting in the
timer I/O control register (TIOR). Rising-edge, falling-edge, or both-edge detection can be
selected. A CPU interrupt request can be issued if the appropriate setting is made in the interrupt
enable register (TIER).
An example of free-running counter and input capture operation is shown in figure 10.14.
In the example in figure 10.14, ATU channel 1 is activated, and input capture operation is
performed with rising-edge detection specified for TIOA1 and both-edge detection for TIOB1.
Rev. 5.00 Jan 06, 2006 page 288 of 818
REJ09B0273-0500
Counter value
TCNT1
STR1
TIOA1
TIOB1
GR1A
GR1B
Input Capture Function
H'FFFF
H'0000
(32 bits in case of channel 0)
H'FFFF
(32 bits in case of channel 0)
H'FFFF
(32 bits in case of channel 0)
Data 1
Data 2
Data 3
Data 4
Figure 10.14 Example of Input Capture Operation
Data 3
Data 1
Data 4
Data 2
Time