HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 340

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 Advanced Timer Unit (ATU)
Sample Setup Procedure for Waveform Output by Output Compare-Match: An example of
the setup procedure for waveform output by output compare-match is shown in figure 10.46.
1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage
2. Set the port E control register (PECR) or port G control register (PGCR), corresponding to the
3. Select 0, 1, or toggle output for output compare-match output with the timer I/O control
4. Set the timing for compare-match generation in the ATU general register (GR) corresponding
5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running
Rev. 5.00 Jan 06, 2006 page 318 of 818
REJ09B0273-0500
counter clock " with the CKSEL bit in the timer control register (TCR). When selecting an
external clock, also select the external clock edge type with the CKEG bit in TCR.
waveform output port, to ATU output compare-match output. Also set the corresponding bit to
1 in the port E IO register (PEIOR) or port G IO register (PGIOR) to specify the output
attribute for the port.
register (TIOR). If necessary, an interrupt request can be sent to the CPU on output compare-
match by making the appropriate setting in the interrupt enable register (TIER).
to the port set in 2.
counter (TCNT). Waveform output is performed from the relevant port when the TCNT value
and GR value match.

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