HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 620

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 19 ROM (256 kB Version)
Bit 0—Program 1 (P1): Selects program mode transition or clearing (applicable addresses:
H'00000 to H'1FFFFF). Do not set the SWE, PSU1, ESU1, EV1, PV1, or E1 bit at the same time.
Bit 0:
P1
0
1
19.5.2
FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode for addresses H'20000 to H'3FFFF is entered by setting SWE (FLMCR1) to
1 when FWE (FLMCR1) = 1, then setting the EV2 or PV2 bit. Program mode for addresses
H'20000 to H'3FFFF is entered by setting SWE (FLMCR1) to 1 when FWE (FLMCR1) = 1, then
setting the PSU2 bit, and finally setting the P2 bit. Erase mode for addresses H'20000 to H'3FFFF
is entered by setting SWE (FLMCR1) to 1 when FWE (FLMCR1) = 1, then setting the ESU2 bit,
and finally setting the E2 bit. FLMCR2 is initialized to H'00 by a reset, in hardware standby mode
and software standby mode, when a low level is input to the FWE pin, and when a high level is
input to the FWE pin and the SWE bit in FLMCR1 is not set (the exception is the FLER bit, which
is initialized only by a reset and in hardware standby mode). When on-chip flash memory is
disabled, a read will return H'00, and writes are invalid.
Writes to bits SWE, ESU2, PSU2, EV2, and PV2 in FLMCR2 are enabled only when FWE
(FLMCR1) = 1 and SWE (FLMCR1) = 1; writes to the E2 bit only when FWE (FLMCR1) = 1,
SWE (FLMCR1) = 1, and ESU2 = 1; and writes to the P2 bit only when FWE (FLMCR1) = 1,
SWE (FLMCR1) = 1, and PSU2 = 1.
Rev. 5.00 Jan 06, 2006 page 598 of 818
REJ09B0273-0500
Initial value:
Flash Memory Control Register 2 (FLMCR2)
Description
Program mode cleared
Transition to program mode
[Setting condition]
When FWE = 1, SWE = 1, and PSU1 = 1
R/W:
Bit:
FLER
R
7
0
R
6
0
ESU2
R/W
5
0
PSU2
R/W
4
0
R/W
EV2
3
0
R/W
PV2
2
0
R/W
E2
1
0
(Initial value)
R/W
P2
0
0

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