HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 92
![MCU 5V 256K J-TEMP PB-FREE QFP-1](/photos/28/62/286212/168-bqfp_sml.jpg)
HD64F7051SFJ20V
Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet
1.HD64F7050SFJ20V.pdf
(843 pages)
Specifications of HD64F7051SFJ20V
Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 92 of 843
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Section 5 Exception Processing
5.5.3
An instruction placed immediately after a delayed branch instruction is said to be placed in a delay
slot. When the instruction placed in the delay slot is undefined code, illegal slot exception
processing starts up when that undefined code is decoded. Illegal slot exception processing also
starts up when an instruction that rewrites the program counter (PC) is placed in a delay slot. The
processing starts when the instruction is decoded. The CPU handles an illegal slot instruction as
follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the jump address of the
3. The exception service routine start address is fetched from the exception processing vector
5.5.4
When undefined code placed anywhere other than immediately after a delayed branch instruction
(i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. The
CPU handles general illegal instructions the same as illegal slot instructions. Unlike processing of
illegal slot instructions, however, the program counter value stored is the start address of the
undefined code.
Rev. 5.00 Jan 06, 2006 page 70 of 818
REJ09B0273-0500
delayed branch instruction immediately before the undefined code or the instruction that
rewrites the PC.
table that corresponds to the exception that occurred. That address is jumped to and the
program starts executing. The jump that occurs is not a delayed branch.
Illegal Slot Instructions
General Illegal Instructions
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