HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 209

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The reload function can be executed whether the transfer data size is 8, 16, or 32 bits.
DMATCR2, which specifies the number of transfers, is decremented by 1 at the end of every
single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore,
when using the reload function in the on state, a multiple of 4 must be specified in DMATCR2.
Operation will not be guaranteed if any other value is set. Also, the counter which counts the
occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR
or the DE bit in CHCR2, setting of the transfer end flag (the TE bit in CHCR2), NMI input, and
setting of the AE flag (address error generation in DMAC transfer), as well as by a reset and in
software standby mode, but SAR2, DAR2, DMATCR2, and other registers are not reset.
Consequently, when one of these sources occurs, there is a mixture of initialized counters and
uninitialized registers in the DMAC, and incorrect operation may result if a restart is executed in
this state. Therefore, when one of the above sources, other than TE setting, occurs during use of
the address reload function, SAR, DAR2, and DMATCR2 settings must be carried out before re-
execution.
address bus
data bus
Internal
Internal
CK
SAR2
1st channel 2
DAR2 output
SAR2 output
Figure 9.26 Source Address Reload Function Timing Chart
transfer
DAR2
SAR2 data
SAR2+2
2nd channel 2
SAR2+2 output
DAR2 output
transfer
DAR2
After SAR2+6 output, SAR2 is reloaded
SAR2+2 data
SAR2+4
SAR2+4 output
3rd channel 2
DAR2 output
Section 9 Direct Memory Access Controller (DMAC)
transfer
DAR2
SAR2+4 data
SAR2+6
SAR2+6 output
Rev. 5.00 Jan 06, 2006 page 187 of 818
4th channel 2
DAR2 output
transfer
DAR2
SAR2+6 data
Bus right is returned one time in four
REJ09B0273-0500
SAR2
5th channel 2
DAR2 output
SAR2 output
transfer
SAR2 data
DAR2