HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 99

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
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Quantity:
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Part Number:
HD64F7051SFJ20V
Manufacturer:
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Quantity:
20 000
6.1.3
Table 6.1 shows the INTC pin configuration.
Table 6.1
6.1.4
The INTC has the 10 registers shown in table 6.2. These registers set the priority of the interrupts
and control external interrupt input signal detection.
Table 6.2
Notes: Two access cycles are required for byte access and word access, and four cycles for
Name
Non-maskable interrupt input pin
Interrupt request input pins
Interrupt request output pin
Name
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
Interrupt control register
IRQ status register
longword access.
1. The value when the NMI pin is high is H'8000; when the NMI pin is low, it is H'0000.
2. Only 0 can be written, in order to clear flags.
Pin Configuration
Register Configuration
Pin Configuration
Register Configuration
Abbr.
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
ICR
ISR
Abbreviation
NMI
IRQ0–IRQ7
IRQOUT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R(W) *
2
Initial Value
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
H'0000
*
H'0000
1
I/O
I
I
O
Rev. 5.00 Jan 06, 2006 page 77 of 818
Function
Input of non-maskable interrupt
request signal
Input of maskable interrupt request
signals
Output of notification signal when an
interrupt has occurred
Section 6 Interrupt Controller (INTC)
Address
H'FFFF8348
H'FFFF834A
H'FFFF834C
H'FFFF834E
H'FFFF8350
H'FFFF8352
H'FFFF8354
H'FFFF8356
H'FFFF8358
H'FFFF835A
REJ09B0273-0500
Access Sizes
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32

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