HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 270

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Advanced Timer Unit (ATU)
Bit 0—Input Capture/Compare-Match Flag (IMF5A): Status flag that indicates GR5A input
capture or compare-match.
Bit 0:
IMF5A
0
1
Timer Status Register E (TSRE)
TSRE indicates the status of channel 6 to 9 cycle register compare-matches.
Note:
Bit 7—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 6—Cycle Register Compare-Match Flag (CMF6): Status flag that indicates CYLR6
compare-match.
Bit 6:
CMF6
0
1
Rev. 5.00 Jan 06, 2006 page 248 of 818
REJ09B0273-0500
Initial value:
* Only 0 can be written, to clear the flag.
Description
[Clearing condition]
When IMF5A is read while set to 1, then 0 is written in IMF5A
[Setting conditions]
Description
[Clearing conditions]
[Setting condition]
When TCNT6 = CYLR6
R/W:
Bit:
When the TCNT5 value is transferred to GR5A by an input capture signal while
GR5A is functioning as an input capture register
When TCNT5 = GR5A while GR5A is functioning as an output compare register
When CMF6 is read while set to 1, then 0 is written in CMF6
When cleared by the DMAC after data transfer when used as a
DMAC activation source
—
R
7
0
R/(W) *
CMF6
6
0
—
R
5
0
R/(W) *
CMF7
4
0
—
R
3
0
R/(W) *
CMF8
2
0
—
R
1
0
(Initial value)
(Initial value)
R/(W) *
CMF9
0
0