HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 157

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.1
The SH7050 series includes an on-chip four-channel direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed data transfers among external
devices equipped with DACK (transfer request acknowledge signal), external memories, memory-
mapped external devices, and on-chip peripheral modules (except for the DMAC, DTC, BSC, and
UBC). Using the DMAC reduces the burden on the CPU and increases operating efficiency of the
LSI as a whole.
9.1.1
The DMAC has the following features:
Four channels
Four GB of address space in the architecture
Byte, word, or longword selectable data transfer unit
16 MB (6,777,216 maximum) transfers
Single or dual address mode. Dual address mode can be direct or indirect address transfer.
Channel function: Transfer modes that can be set are different for each channel. (Dual address
mode indirect access can only be set for channel 1. Only direct access is possible for the other
channels).
Section 9 Direct Memory Access Controller (DMAC)
Single address mode: Either the transfer source or transfer destination (peripheral device) is
accessed by a DACK signal while the other is accessed by address. One transfer unit of
data is transferred in each bus cycle.
Dual address mode: Both the transfer source and transfer destination are accessed by
address. Dual address mode can be direct or indirect address transfer.
•
•
Channel 0: Single or dual address mode. External requests are accepted.
Channel 1: Single or dual address mode. External requests are accepted.
Channel 2: Dual address mode only. Source address reload function operates every fourth
transfer.
Features
Overview
Direct access: Values set in a DMAC internal register indicate the accessed address for
both the transfer source and transfer destination. Two bus cycles are required for one
data transfer.
Indirect access: The value stored at the location pointed to by the address set in the
DMAC internal transfer source register is used as the address. Operation is otherwise
the same as direct access. This function can only be set for channel 3.
Section 9 Direct Memory Access Controller (DMAC)
Rev. 5.00 Jan 06, 2006 page 135 of 818
REJ09B0273-0500