HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 405

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 3—Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to a
parity error in the asynchronous mode.
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, the TDR did not contain valid data, so transmission has ended. TEND is a read-only
bit and cannot be written.
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a
read-only bit and cannot be written.
Bit 3: PER
0
1
Bit 2: TEND
0
1
Bit 1: MPB
0
1
Description
Receiving is in progress or has ended normally (initial value). Clearing the RE bit
to 0 in the serial control register does not affect the PER bit, which retains its
previous value.
PER is cleared to 0 when the chip is power-on reset or enters standby mode or
software reads PER after it has been set to 1, then writes 0 in PER
A receive parity error occurred. When a parity error occurs, the SCI transfers the
receive data into the RDR but does not set RDRF. Serial receiving cannot
continue while PER is set to 1. In the clock synchronous mode, serial
transmitting is also disabled.
PER is set to 1 if the number of 1s in receive data, including the parity bit, does
not match the even or odd parity setting of the parity mode bit (O/E) in the serial
mode register (SMR)
Description
Transmission is in progress
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 in TDRE, or the DMAC writes data in TDR
End of transmission (initial value)
TEND is set to 1 when the chip is power-on reset or enters standby mode, TE is
cleared to 0 in the serial control register (SCR), or TDRE is 1 when the last bit of
a one-byte serial character is transmitted.
Description
Multiprocessor bit value in receive data is 0 (initial value). If RE is cleared to 0
when a multiprocessor format is selected, the MPB retains its previous value.
Multiprocessor bit value in receive data is 1
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 06, 2006 page 383 of 818
REJ09B0273-0500