HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 218

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Advanced Timer Unit (ATU)
Rev. 5.00 Jan 06, 2006 page 196 of 818
REJ09B0273-0500
Channels 6 to 9 have four PWM outputs, allowing the following operations:
Channel 10 has eight 16-bit down-counters for one-shot pulse output, allowing the following
operations:
High-speed access to internal 16-bit bus
44 interrupt sources
Direct memory access controller (DMAC) activation
A/D converter activation
Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle
output
Input capture function: Rising-edge, falling-edge, or both-edge detection
Ten compare-match interrupts/capture interrupts (channel 3/A–D, channel 4/A–D, channel
5/A, B) and three counter overflow interrupts can be generated
Any cycle and duty from 0 to 100% can be set
Duty buffer register, with transfer to duty register every cycle
Interrupts can be generated every cycle
One-shot pulse generation by down-counter
Down-counter can be rewritten during count
Interrupt can be generated at end of down-count
Offset one-shot pulse function available
High-speed access to 16-bit bus for 16-bit registers: timer counters, compare registers, and
capture registers
Four input capture and one overflow interrupt request for channel 0
Four interval interrupt requests
Eight dual input capture/compare-match interrupt requests and two counter overflow
interrupt requests for channels 1 and 2
Ten dual input capture/compare-match interrupt requests and three overflow interrupt
requests for channels 3 to 5
Four cycle interrupts for channels 6 to 9
Eight underflow interrupts for channel 10
The DMAC can be activated by a channel 0 input capture interrupt (ICI0B)
The DMAC can be activated by a channel 6 cycle register 6 compare-match interrupt
(CMI6)
The A/D converter can be activated by detection of 1 in bits 10 to 13 of the channel 0 free-
running counter (TCNT0)