HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 384

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Watchdog Timer (WDT)
Reading from the TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like
other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for the TCSR,
H'FFFF8611 for the TCNT, and H'FFFF8613 for the RSTCSR.
12.3
12.3.1
To use the WDT as a watchdog timer, set the WT/IT and TME bits of the TCSR to 1. Software
must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. No TCNT overflows will occur while the system is operating normally, but if the
TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF
signal is output externally (figure 12.4). The WDTOVF signal can be used to reset the system. The
WDTOVF signal is output for 128 clock cycles.
If the RSTE bit in the RSTCSR is set to 1, a signal to reset the chip will be generated internally
simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual
reset can be selected by the RSTS bit. The internal reset signal is output for 512 clock cycles.
When a watchdog overflow reset is generated simultaneously with a reset input at the RES pin, the
RES reset takes priority, and the WOVF bit is cleared to 0.
The following are not initialized a WDT reset signal:
Initializing is only possible by external power-on reset.
Rev. 5.00 Jan 06, 2006 page 362 of 818
REJ09B0273-0500
PFC (Pin Function Controller) function register
I/O port register
Operation
Watchdog Timer Mode
Writing 0 to the WOVF bit
Writing to the RSTE bit
Address:
Address:
Figure 12.3 Writing to the RSTCSR
H'FFFF8612
H'FFFF8612
15
15
H'A5
H'5A
8
8
7
7
Write data
H'00
0
0