HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 391

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.1
The SH7050 series has a serial communication interface (SCI) with three independent channels,
both of which possess the same functions.
The SCI supports both asynchronous and clock synchronous serial communication. It also has a
multiprocessor communication function for serial communication among two or more processors.
13.1.1
Select asynchronous or clock synchronous as the serial communications mode.
Asynchronous mode: Serial data communications are synched by start-stop in character units.
The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an
asynchronous communication interface adapter (ACIA), or any other chip that employs a
standard asynchronous serial communication. It can also communicate with two or more other
processors using the multiprocessor communication function. There are twelve selectable
serial data communication formats.
Clocked synchronous mode: Serial data communication is synchronized with a clock signal.
The SCI can communicate with other chips having a clock synchronous communication
function. There is one serial data communication format.
Full duplex communication: The transmitting and receiving sections are independent, so the
SCI can transmit and receive simultaneously. Both sections use double buffering, so
continuous data transfer is possible in both the transmit and receive directions.
On-chip baud rate generator with selectable bit rates.
Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin
(external).
Data length: seven or eight bits
Stop bit length: one or two bits
Parity: even, odd, or none
Multiprocessor bit: one or none
Receive error detection: parity, overrun, and framing errors
Break detection: by reading the RxD level directly when a framing error occurs
Data length: eight bits
Receive error detection: overrun errors
Section 13 Serial Communication Interface (SCI)
Overview
Features
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 06, 2006 page 369 of 818
REJ09B0273-0500