HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 522

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 16 Pin Function Controller (PFC)
16.3.9
The port E IO register (PEIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 15 pins in port E. Bits PE14IOR to PE0IOR correspond to pins PE14/TIOC3 to
PE0/TIOA1. PEIOR is enabled when port E pins function as general input/output pins (PE14 to
PE0) or as ATU input/output pins, and disabled otherwise. PEIOR bits 8 to 11 should be cleared to
0 when ATU input capture input is selected.
When port E pins function as PE14 to PE0, a pin becomes an output when the corresponding bit in
PEIOR is set to 1, and an input when the bit is cleared to 0.
PEIOR is initialized to H'8000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
16.3.10 Port E Control Register (PECR)
The port E control register (PECR) is a 16-bit readable/writable register that selects the functions
of the 15 multiplex pins in port E.
PECR is initialized to H'8000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Bit 15—Reserved: This bit is always read as 1, and should only be written with 1.
Rev. 5.00 Jan 06, 2006 page 500 of 818
REJ09B0273-0500
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Port E IO Register (PEIOR)
15
15
R
R
1
1
PE14
PE14
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
IOR
MD
14
14
0
0
PE13
PE13
IOR
MD
13
13
0
0
PE12
PE12
IOR
MD
12
12
0
0
PE11
PE11
IOR
MD
11
11
0
0
PE10
PE10
IOR
MD
10
10
0
0
PE9
PE9
IOR
MD
9
0
9
0
PE8
PE8
IOR
MD
8
0
8
0
PE7
PE7
IOR
MD
7
0
7
0
PE6
PE6
IOR
MD
6
0
6
0
PE5
PE5
IOR
MD
5
0
5
0
PE4
PE4
IOR
MD
4
0
4
0
PE3
PE3
IOR
MD
3
0
3
0
PE2
PE2
IOR
MD
2
0
2
0
PE1
PE1
IOR
MD
1
0
1
0
PE0
PE0
IOR
MD
0
0
0
0

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