HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 427

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In receiving, the SCI operates as follows:
1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes
2. Receive data is shifted into the RSR in order from the LSB to the MSB.
3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following
4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
Figure 13.9 shows an example of SCI receive operation in the asynchronous mode.
Table 13.11 Receive Error Conditions and SCI Operation
Receive Error
Overrun error
Framing error
Parity error
internally and starts receiving.
checks:
a. Parity check. The number of 1s in the receive data must match the even or odd parity
b. Stop bit check. The stop bit value must be 1. If there are two stop bits, only the first stop bit
c. Status check. RDRF must be 0 so that receive data can be loaded from the RSR into the
If the data passes these checks, the SCI sets RDRF to 1 and stores the received data in the
RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 13.11.
Note: When a receive error occurs, further receiving is disabled. While receiving, the RDRF
SCR, the SCI requests a receive-data-full interrupt (RxI). If one of the error flags (ORER,
PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCR is also
set to 1, the SCI requests a receive-error interrupt (ERI).
setting of the O/E bit in the SMR.
is checked.
RDR.
bit is not set to 1, so be sure to clear the error flags.
Abbreviation
FER
PER
ORER
Condition
Receiving of next data ends while
RDRF is still set to 1 in SSR
Stop bit is 0
Parity of receive data differs from
even/odd parity setting in SMR
Section 13 Serial Communication Interface (SCI)
Rev. 5.00 Jan 06, 2006 page 405 of 818
Data Transfer
Receive data not loaded
from RSR into RDR
Receive data loaded from
RSR into RDR
Receive data loaded from
RSR into RDR
REJ09B0273-0500