HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 571

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.5.4
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'0000 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode. (For details, see the description of the BSC.)
Flash memory area divisions are shown in table 18.4. To ensure correct operation of the emulation
function, the ROM for which RAM emulation is performed should not be accessed immediately
after this register has been modified. Normal execution of an access immediately after register
modification is not guaranteed.
Bits 15 to 3—Reserved: These bits are always read as 0.
Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bits 1 and 0—Flash Memory Area Selection (RAM1, RAM0): These bits are used together
with bit 2 to select the flash memory area to be overlapped with RAM. (See table 18.4.)
Bit 2:
RAMS
0
1
Initial value:
Initial value:
RAM Emulation Register (RAMER)
Description
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
R/W:
R/W:
Bit:
Bit:
15
—
—
R
R
0
7
0
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
Rev. 5.00 Jan 06, 2006 page 549 of 818
11
—
—
R
R
Section 18 ROM (128 kB Version)
0
3
0
RAMS
R/W
10
—
R
0
2
0
REJ09B0273-0500
RAM1
R/W
—
R
9
0
1
0
(Initial value)
RAM0
R/W
—
R
8
0
0
0