HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 251

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TIOR2A is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit 7—Reserved: This bit is always read as 0, and should only be written with 0.
Bits 6 to 4—I/O Control 1B2 to 1B0, 1D2 to 1D0, 1F2 to 1F0, 2B2 to 2B0 (IO1B2 to IO1B0,
IO1D2 to IO1D0, IOF12 to IO1F0, IO2B2 to IO2B0): These bits select the general register
(GR) function.
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Bits 2 to 0—I/O Control 1A2 to 1A0, 1C2 to 1C0, 1E2 to 1E0, 2A2 to 2A0 (IO1A2 to IO1A0,
IO1C2 to IO1C0, IO1E2 to IO1E0, IO2A2 to IO2A0): These bits select the general register
(GR) function.
Bit 6:
IOxx2
0
1
Bit 5:
IOxx1
0
1
0
1
Bit 4:
IOxx0
0
1
0
1
0
1
0
1
Description
GR is an output
compare register
GR is input capture
register
0 output regardless of compare-match
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge
Input capture in GR on falling edge
Input capture in GR on both rising and
falling edges
Rev. 5.00 Jan 06, 2006 page 229 of 818
Section 10 Advanced Timer Unit (ATU)
REJ09B0273-0500
(Initial value)