HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 501

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3
16.3.1
The port A IO register (PAIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port A. Bits PA15IOR to PA0IOR correspond to pins PA15/A15 to
PA0/A0. PAIOR is enabled when port A pins function as general input/output pins (PA15 to
PA0), and disabled otherwise.
When port A pins function as PA15 to PA0, a pin becomes an output when the corresponding bit
in PAIOR is set to 1, and an input when the bit is cleared to 0.
PAIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
16.3.2
The port A control register (PACR) is a 16-bit readable/writable register that selects the functions
of the 16 multiplex pins in port A. PACR settings are not valid in all operating modes.
1. Expanded mode with on-chip ROM disabled
2. Expanded mode with on-chip ROM enabled
3. Single-chip mode
Initial value:
Initial value:
Port A pins function as address output pins, and PACR settings are invalid.
Port A pins are multiplexed as address output pins and general input/output pins. PACR
settings are valid.
Port A pins function as general input/output pins, and PACR settings are invalid.
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Bit:
Register Descriptions
Port A IO Register (PAIOR)
Port A Control Register (PACR)
PA15
PA15
IOR
MD
15
15
0
0
PA14
PA14
IOR
MD
14
14
0
0
PA13
PA13
IOR
MD
13
13
0
0
PA12
PA12
IOR
MD
12
12
0
0
PA11
PA11
IOR
MD
11
11
0
0
PA10
PA10
IOR
MD
10
10
0
0
PA9
PA9
IOR
MD
9
0
9
0
PA8
PA8
IOR
MD
8
0
8
0
Section 16 Pin Function Controller (PFC)
PA7
PA7
IOR
MD
Rev. 5.00 Jan 06, 2006 page 479 of 818
7
0
7
0
PA6
PA6
IOR
MD
6
0
6
0
PA5
PA5
IOR
MD
5
0
5
0
PA4
PA4
IOR
MD
4
0
4
0
PA3
PA3
IOR
MD
3
0
3
0
REJ09B0273-0500
PA2
PA2
IOR
MD
2
0
2
0
PA1
PA1
IOR
MD
1
0
1
0
PA0
PA0
IOR
MD
0
0
0
0