mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 107

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

6.2.3
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the MCU are not exceeded. Drive strength selection affects the
DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive a
greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this,
the EMC emissions may be affected by enabling pins as high drive.
6.3
The V1 ColdFire core is capable of performing higher speed I/O via its local bus, which does not have
latency penalties associated with the on-chip peripheral bus bridge. The rapid GPIO module contains
separate set/clear/data registers which are based at address 0x(00)C0_0000. This functionality can be
programmed to take priority on ports E and F.
This functionality is further defined in
6.4
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
6.5
This section provides information about the registers associated with the parallel I/O ports. The data and
data direction registers and the keyboard interrupt registers are located in page zero of the memory map.
The pullup, slew rate, drive strength, and interrupt control registers are located in the high page section of
the memory map.
Refer to tables in
pin control registers. This section refers to registers and control bits only by their names. A Freescale
Freescale Semiconductor
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Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was executed (port states are lost and will need to be restored upon
exiting stop2). CPU register status and the state of I/O registers must be saved in RAM before the
STOP instruction is executed to place the MCU in stop2 mode.
Upon recovery from stop2 mode, before accessing any I/O, the user must examine the state of the
SPMSC2[PPDF] bit. If the PPDF bit is cleared, I/O must be initialized as if a power-on-reset had
occurred. If the PPDF bit is set, I/O register states must be restored from the values saved in RAM
before the STOP instruction was executed and peripherals may require initialization or restoration
to their pre-stop condition. The user must then write a 1 to the SPMSC2[PPDACK] bit. Access to
I/O is now permitted again in the user application program.
In stop3 and stop4 modes, all I/O is maintained because internal logic circuity stays powered. Upon
recovery, normal I/O function is available to the user.
V1 ColdFire Rapid GPIO Functionality
Pin Behavior in Stop Modes
Register Definition
Port Drive Strength Select
Chapter 4,
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
“Memory,” for the absolute address assignments for all parallel I/O and their
Chapter 17, “Rapid GPIO (RGPIO).”
Parallel Input/Output Control
6-3