mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 358

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale’s Controller Area Network (MSCANV1)
15.5.4
15.5.4.1
The MSCAN module behaves as described within this specification in all normal system operation modes.
15.5.4.2
The MSCAN module behaves as described within this specification in all special system operation modes.
15.5.4.3
In all emulation modes, the MSCAN module behaves just like normal system operation modes as
described within this specification.
15.5.4.4
In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames
and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a
transmision. If the MAC sub-layer is required to send a “dominant” bit (ACK bit, overload flag, or active
error flag), the bit is rerouted internally so that the MAC sub-layer monitors this “dominant” bit, although
the CAN bus may remain in recessive state externally.
15.5.4.5
The MSCAN module has no security features.
15.5.4.6
Loopback self test mode is sometimes used to check software, independent of connections in the external
system, to help isolate system problems. In this mode, the transmitter output is internally connected to the
receiver input. The RXCAN input pin is ignored and the TXCAN output goes to the recessive state (logic
1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as
a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot
15-42
Time Segment 1
Modes of Operation
Normal Modes
Special Modes
Emulation Modes
Listen-Only Mode
Security Modes
Loopback Self Test Mode
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 15-35. CAN Standard Compliant Bit Time Segment Settings
TSEG1
3 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
4 .. 9
Time Segment 2
2
3
4
5
6
7
8
TSEG2
1
2
3
4
5
6
7
Synchronization
Jump Width
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
Freescale Semiconductor
SJW
0 .. 1
0 .. 2
0 .. 3
0 .. 3
0 .. 3
0 .. 3
0 .. 3

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