mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 225

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

11.3.17 FTM Channels Polarity Register (FTMxPOL)
This read/write register defines the output polarity of the FTM channels.
11.3.18 FTM Fault Mode Status Register (FTMxFMS)
This read/write register contains the fault detection flag, write protection enable and the fault input bits.
Freescale Semiconductor
Reset
where j = 7, 6,
INITTRIGEN
W
R
CHjTRIG
5, 4, 3, 2
TRIGF
POLn
Field
Field
5-0
7-0
7
6
POL7
0
7
The safe value that is driven in the channel (n) output when the fault control
is enabled and a fault condition is detected is the inactive state of the channel
(n) polarity. The channel (n) safe value is the value of its POL bit.
Channel trigger flag. This read/write bit is set when a channel trigger is generated. Clear TRIGF bit by
reading FTMxEXTTRIG while TRIGF is set and then writing a logic 0 to TRIGF. If another channel
trigger is generated before the clearing sequence is complete, the sequence is reset so TRIGF remains
set after the clear sequence is completed for the earlier TRIGF.
Reset clears TRIGF. Writing a logic 1 to TRIGF has no effect.
0 No channel trigger was generated
1 A channel trigger was generated
Initialization trigger enable. This read/write bit enables the generation of the trigger when the FTM
counter is equal to its initial value.
0 The generation of initialization trigger is disabled
1 The generation of initialization trigger is enabled
Channel j trigger enable. These read/write bits enable the generation of a channel trigger when the FTM
counter is equal to the FTMxC(j)VH:FTMxC(j)VL registers. Several FTM channels can be selected to
generate multiple triggers in one PWM period.
0 The generation of channel (j) trigger is disabled.
1 The generation of channel (j) trigger is enabled.
Channel (n) polarity. The POLn bit defines the polarity of the channel (n) output.
POLn is write protected, this bit can only be written if WPDIS = 1.
0 The channel (n) polarity is high (the active state is logical one and the inactive state is logical zero).
1 The channel (n) polarity is low (the active state is logical zero and the inactive state is logical one).
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
= Unimplemented or Reserved
POL6
Figure 11-20. FTM Channels Polarity Register (FTMxPOL)
0
6
Table 11-18. FTMxEXTTRIG Field Descriptions
Table 11-19. FTMxPOL Field Descriptions
POL5
5
0
POL4
0
4
NOTE
Description
Description
POL3
0
3
POL2
0
2
POL1
FlexTimer Module (FTMV1)
1
0
POL0
0
0
11-25