mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 283

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

12.4.1.1
When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a
master may initiate communication by sending a start signal. As shown in
defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new
data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle
states.
12.4.1.2
The first byte of data transferred immediately after the start signal is the slave address transmitted by the
master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
Only the slave with a calling address that matches the one transmitted by the master responds by sending
back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see
No two slaves in the system may have the same address. If the IIC module is the master, it must not
transmit an address equal to its own slave address. The IIC cannot be master and slave at the same time.
However, if arbitration is lost during an address cycle, the IIC reverts to slave mode and operates correctly
even if it is being addressed by another master.
Freescale Semiconductor
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
SCL
SDA
SCL
SDA
Signal
Signal
Start
Start
Start Signal
Slave Address Transmission
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
1
1
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
2
2
Calling Address
Calling Address
3
3
4
4
5
5
Figure 12-8. IIC Bus Transmission Signals
6
6
7
7
Read/
Read/
Write
Write
lsb
lsb
8
8
Ack
Ack
Bit
9
Bit
9
XX
Repeated
XXX
Signal
Start
msb
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
D7
1
1
D6
2
2
New Calling Address
D5
3
3
Data Byte
D4
4
4
D3
Figure
5
5
D2
6
6
Inter-Integrated Circuit (IICV2)
12-8, a start signal is
D1
7
7
Read/
Write
lsb
lsb
Figure
D0
8
8
Ack
No
Bit
Ack
No
9
Bit
9
12-8).
Signal
Stop
Signal
Stop
12-11