mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 91

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

5.5.4
The LVD system has a low voltage warning flag (LVWF) to indicate to the user that the supply voltage is
approaching, but is above, the LVD voltage. LVWF is cleared by writing a 1 to the SPMSC2[LVWACK]
bit. There are two user-selectable trip voltages for the LVW, one high (V
trip voltage is selected by SPMSC2[LVWV] bit.
5.6
The real-time interrupt function can be used to generate periodic interrupts. The RTI can accept two
sources of clocks, the 1 kHz low power oscillator or the external oscillator if available. The 1 kHz internal
clock source is completely independent of any bus clock source and is used only by the RTI module and,
on some MCUs, the COP watchdog. The external clock source is the external reference of the MCG. To
use the external oscillator as the RTI clock, it must be available and active. The RTICLKS bit in SRTISC
is used to select the RTI clock source.
Either RTI clock source can be used when the MCU is in run, wait or stop3 mode. When using the external
oscillator in stop3, it must be enabled in stop (OSCSTEN = 1). Only the internal 1 kHz clock source can
be selected to wake the MCU from stop2 mode.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS2:RTIS1:RTIS0) used to disable the clock source to the real-time interrupt or select one of
seven wakeup periods. The RTI has a local interrupt enable, RTIE, to allow masking of the real-time
interrupt. The RTI can be disabled by writing each bit of RTIS to zeroes, and no interrupts will be
generated. See
detailed information about this register.
5.7
The PTC2 pin is shared with the MCLK clock output. Setting the pin enable bit, MPE, causes the PTC2
pin to output a divided version of the internal MCU bus clock. The divide ratio is determined by the
MCSEL bits. When MPE is set, the PTC2 pin is forced to operate as an output pin regardless of the state
of the port data direction control bit for the pin. If the MCSEL bits are all 0s, the pin will be driven low.
The slew rate and drive strength for the pin are controlled by PTCSE2 and PTCDS2, respectively. The
maximum clock output frequency is limited if slew rate control is enabled, see the data sheet for pin rise
and fall times with slew rate enabled.
5.8
The MCF51AC256 series microcontrollers include a clock gating system to manage the bus clock sources
to the individual peripherals. Using this system, the user can enable or disable the bus clock to each
peripheral at the clock source, eliminating unnecessary clocks to peripherals which are not in use; thereby
reducing the overall run and wait mode currents.
Out of reset, all peripheral clocks will be enabled. For lowest possible run or wait currents, user software
must disable the clock source to any peripheral not in use. The actual clock will be enabled or disabled
immediately following the write to the clock gating control registers (SCGC1, SCGC2). Any peripheral
Freescale Semiconductor
Real-Time Interrupt (RTI)
MCLK Output
Peripheral Clock Gating
Low-Voltage Warning (LVW) Operation
Section 5.9.6, “System Real-Time Interrupt Status and Control Register
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Resets, Interrupts, and General System Control
LVWH
) and one low (V
(SRTISC),” for
LVWL
). The
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