mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 82

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Memory
4-38
1
1. The last three steps are optional, but recommended.
Write CSR2[25:24]=11 to initiate BDM reset to halt or
write CSR2[25:24]=01 to initiate BDM reset to run
Hold BKGD=0, apply power, wait N+16 cycles
FEI 10 MHz clock, synchronized to debugger
Set PRDIV8 and clock divider fields in CSR3
Write XCSR[31:24] = 0x87 to initiate
Secure state unknown, CPU halted,
Secure state unknown, CPU halted,
On-chip flash is erased and secure
Secure state unknown/unpowered
FEI 10 MHz clock, SYNC required
erase/verify of flash memory
Read XCSR[25] to confirm
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
erase/verify complete
for POR to deassert
Device is unsecure
Figure 4-15. Procedure for Clearing Security via the BDM Port
Delay ‘TBD’ cycles
Read XCSR
SYNC
?
XCSR[31:24] = 0x87
Yes
No
XCSR[31:24] ≠ 1000_01x1
XCSR[25] = 0
N = number of cycles for SIM to release internal
reset. Adder of 16 imposed by ColdFire core.
BKGD=0 during reset will ensure that
ENBDM comes up ‘1’.
FLL enabled, internal reference (FEI)
at 10MHz is reset default for the ICS.
Note: The write is required.
Of these, only method 1 is guaranteed
to work under all circumstances.
Ways to enter BDM halt mode:
1. BKGD=0 during POR
2.
3.
4.
5.
6.
7.
8.
BKGD=0 during external reset
BKGD=0 during BDM reset
BFHBR=1 during BDM reset
Issue BACKGROUND command
via BDM interface
HALT instruction
BDM breakpoint
ColdFire fault-on-fault
STOP
Already
unsecured.
STOP
Error condition
check code or device.
Freescale Semiconductor