mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 154

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

ColdFire Core
7.3.4.2
Table 7-14
7-24
4. All operand data accesses are aligned on the same byte boundary as the operand size; for example,
(d8,Ay,Xi*SF)
16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4
addresses.
The processor core decomposes misaligned operand references into a series of aligned accesses as
shown in
(d16,Ay)
Source
xxx.w
(Ay)+
-(Ay)
xxx.l
(Ay)
Dy
Ay
lists execution times for MOVE.{B,W} instructions;
MOVE Instruction Execution Times
For all tables in this section, the execution time of any instruction using the
PC-relative effective addressing modes is the same for the comparable
An-relative mode.
The nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w
and xxx.l.
Table
ET with {<ea> = (d16,PC)}
ET with {<ea> = (d8,PC,Xi*SF)}
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
1(0/0)
1(0/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
2(1/0)
2(1/0)
7-13.
Rx
address[1:0]
Table 7-14. MOVE Byte and Word Execution Times
01 or 11
01 or 11
Table 7-13. Misaligned Operand References
10
3(1/1)
3(1/1)
3(1/1)
1(0/1)
1(0/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
(Ax)
Word
Long
Long
Size
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
3(1/1)
(Ax)+
NOTE
equals ET with {<ea> = (d16,An)}
equals ET with {<ea> = (d8,An,Xi*SF)}
Operations
Word, Word
Byte, Word,
Destination
Byte, Byte
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
4(1/1)
3(1/1)
3(1/1)
Byte
-(Ax)
Bus
Table 7-15
(d16,Ax)
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
3(1/1)
1(0/1) if write
2(0/2) if write
1(0/1) if write
2(1/0) if read
3(2/0) if read
2(1/0) if read
Additional
—
—
—
C(R/W)
lists timings for MOVE.L.
(d8,Ax,Xi*SF)
4(1/1))
4(1/1))
4(1/1))
2(0/1)
2(0/1)
—
—
—
—
Freescale Semiconductor
xxx.wl
1(0/1)
1(0/1)
3(1/1)
3(1/1)
3(1/1)
—
—
—
—