mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 421

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
in progress must first be completed. This includes data characters in progress, queued idle characters, and
queued break characters.
18.3.2.1
The SBK control bit in SCIxC2 sends break characters originally used to gain the attention of old teletype
receivers. Break characters are a full character time of logic 0 (10 bit times including the start and stop
bits). A longer break of 13 bit times can be enabled by setting BRK13. Normally, a program would wait
for TDRE to become set to indicate the last character of a message has moved to the transmit shifter, then
write 1 and then write 0 to the SBK bit. This action queues a break character to be sent as soon as the shifter
is available. If SBK remains 1 when the queued break moves into the shifter (synchronized to the baud rate
clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor
SCI, the break characters are received as 0s in all eight data bits and a framing error (FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not finish while TE is cleared, the SCI transmitter never actually releases control of the TxD
pin. If there is a possibility of the shifter finishing while TE is cleard, set the general-purpose I/O controls
so the pin shared with TxD is an output driving a logic 1. This ensures that the TxD line looks like a normal
idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
The length of the break character is affected by the BRK13 and M bits as shown below.
18.3.3
In this section, the receiver block diagram
description. Next, the data sampling technique used to reconstruct receiver data is described in more detail.
Finally, two variations of the receiver wakeup function are explained.
The receiver input is inverted by setting RXINV. The receiver is enabled by setting the RE bit in SCIxC2.
Character frames consist of a start bit of logic 0, eight (or nine) data bits (lsb first), and a stop bit of logic
1. For information about 9-bit data mode, refer to
of this discussion, assume the SCI is configured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already
full, the data character is transferred to the receive data register and the receive data register full (RDRF)
Freescale Semiconductor
Receiver Functional Description
Send Break and Queued Idle
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
BRK13
0
0
1
1
Table 18-8. Break Character Length
M
0
1
0
1
(Figure
Serial Communication Interface (SCI)Serial Communications Interface (SCIV4)
Section •, “8- and 9-bit data
18-2) is a guide for the overall receiver functional
Break Character Length
10 bit times
11 bit times
13 bit times
14 bit times
modes”. For the remainder
18-13