mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 310

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Interrupt Controller (CF1_INTC)
If there is a pending non-level seven request, execution continues with a three instruction sequence to
calculate and then branch to the appropriate alternate ISR entry point. This sequence assumes the
exception vector table is based at address 0x(00)00_0000 and that each ISR uses the same two-instruction
prologue shown here. The resulting alternate entry point is a fixed offset (8 bytes) from the normal entry
point defined in the exception vector table.
The ISR epilogue includes a three instruction sequence to restore the volatile registers from the stack and
return from the interrupt exception.
This example is intentionally simple, but does show how performing the software IACK and passing
control to an alternate entry point when there is a pending but masked interrupt request can avoid the
execution of the ISR epilogue, another interrupt exception, and the ISR prologue.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
13-20
Freescale Semiconductor

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