mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 153

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

7.3.4
This section presents processor instruction execution times in terms of processor-core clock cycles. The
number of operand references for each instruction is enclosed in parentheses following the number of
processor clock cycles. Each timing entry is presented as C(R/W) where:
This section includes the assumptions concerning the timing values and the execution time details.
7.3.4.1
For the timing data presented in this section, these assumptions apply:
Freescale Semiconductor
SRAMSZ
Field
•
•
1. The OEP is loaded with the opword and all required extension words at the beginning of each
2. The OEP does not experience any sequence-related pipeline stalls. The most common example of
3. The OEP completes all memory accesses without any stall conditions caused by the memory itself.
7–3
2–0
C is the number of processor clock cycles, including all applicable operand fetches and writes, and
all internal core cycles required to complete the instruction execution.
R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation
performing a read-modify-write function is denoted as (1/1).
instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or
extension words.
stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE
operations (except MOVEM), certain hardware resources within the processor are marked as busy
for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store
instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is
stalled until the resource again becomes available. Thus, the maximum pipeline stall involving
consecutive STORE operations is two cycles. The MOVEM instruction uses a different set of
resources and this stall does not apply.
Thus, the timing details provided in this section assume that an infinite zero-wait state memory is
attached to the processor core.
SRAM bank size.
00000 No SRAM
00010 512 bytes
00100 1 KB
00110 2 KB
01000 4 KB
01010 8 KB
01100 16 KB
01111 24 KB
01110 32 KB (This is the value used for this device)
10000 64 KB
10010 128 KB
Else
Reserved.
Instruction Execution Timing
Table 7-12. D1 Hardware Configuration Information Field Description (continued)
Timing Assumptions
Reserved for future use
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Description
ColdFire Core
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