mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 236

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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FlexTimer Module (FTMV1)
minimum pulse width (CHnFVAL[3:0] x 4 system clocks) plus a further 4 rising edges of the system clock
(two rising edges to the synchronizer, one rising edge to the filter output plus one more to the edge
detector). In other words CHnF is set (4 + 4 x CHnFVAL[3:0]) system clock periods after a valid edge
occurs on the channel input pin.
The clock for the 5-bit counter in the channel input filter is the system clock divided by 4.
11.4.5
The output compare mode is selected when:
In output compare mode, the FTM can generate timed pulses with programmable position, polarity,
duration, and frequency. When the counter matches the value in the FTMxCnVH:FTMxCnVL registers of
an output compare channel, the channel (n) output can be set, cleared or toggled.
When a channel is initially configured to toggle mode, the previous value of the channel output is held
until the first output compare event occurs.
The TOF bit is set and the timer overflow interrupt is generated (if TOIE = 1) at the end of the PWM period
(when the FTM counter changes from FTMxMODH:FTMxMODL to FTMxCNTINH:FTMxCNTINL).
11-36
channel (n) input after
system clock divided by 4
the synchronizer
after the synchronizer
(FTMEN = 0) and (COMBINE = 0) and (CPWMS = 0) and (MSnB:MSnA = 0:1)
CHnFVAL[3:0] = 0010
system clock
channel (n) input
(binary value)
Output compare mode
5-bit counter
filter output
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Logic to control
the filter counter
divided by 4
Figure 11-34. Channel input filter example
Figure 11-33. Channel Input Filter
5-bit up counter
Logic to define
the filter output
CHnFVAL[3:0]
S
C
CLK
Freescale Semiconductor
Q
Time
filter output

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