mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 457

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI control register
1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected.
20.4.2
The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate
transmissions. A transmission begins by reading the SPIxS register while SPTEF = 1 and writing to the
master SPI data registers. If the shift register is empty, the byte immediately transfers to the shift register.
The data begins shifting out on the MOSI pin under the control of the serial clock.
The SPR3, SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and
SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and
determine the speed of the transmission. The SPSCK pin is the SPI clock output. Through the SPSCK pin,
the baud rate generator of the master controls the shift register of the slave peripheral.
In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is
determined by the SPC0 and BIDIROE control bits.
If MODFEN and SSOE bit are set, the SS pin is configured as slave select output. The SS output becomes
low during each transmission and is high when the SPI is in idle state.
If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error.
If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI
and SPSCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and
also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs
are disabled and SPSCK, MOSI and MISO are inputs. If a transmission is in progress when the mode fault
occurs, the transmission is aborted and the SPI is forced into idle state.
This mode fault error also sets the mode fault (MODF) flag in the SPI Status Register (SPIxS). If the SPI
interrupt enable bit (SPIE) is set when the MODF flag gets set, then an SPI interrupt sequence is also
requested.
When a write to the SPI Data Register in the master occurs, there is a half SPSCK-cycle delay. After the
delay, SPSCK is started within the master. The rest of the transfer operation differs slightly, depending on
the clock format specified by the SPI clock phase bit, CPHA, in SPI Control Register 1 (see
“SPI Clock
Freescale Semiconductor
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•
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SPSCK
MOSI, MISO pin
SS pin
Formats”).
Master Mode
A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0,
BIDIROE with SPC0 set, SPIMODE, FIFOMODE, SPPR2-SPPR0 and
SPR3-SPR0 in master mode will abort a transmission in progress and force
the SPI into idle state. The remote slave cannot detect this, therefore the
master has to ensure that the remote slave is set back to idle state.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
NOTE
16-Bit Serial Peripheral Interface (SPI16)
Section 20.4.6,
20-17