mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 253

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

If two or more hardware triggers are enabled (TRIG0 and TRIG1 = 1) and only the trigger 1 event occurs,
then only the TRIG1 bit is cleared.
If a trigger n event occurs together with a write to set the TRIGn bit, then the synchronization is made, but
the TRIGn bit remains set because of the last write.
11.4.11.2 Software trigger
A software trigger event occurs when 1 is written to the SWSYNC bit. The SWSYNC bit is cleared when
0 is written to it or when the PWM synchronization (initiated by the software event) is complete.
If the software trigger event occurs together with the event that clears the SWSYNC bit, then the
synchronization is made using this trigger event and the SWSYNC bit remains set because of the last write.
For example, if REINIT = 0 and there is a software trigger event, then the load of FTMxMODH:L and
FTMxCnVH:L reigsters is only made at the boundary cycle (CNTMIN and CNTMAX). In this case, the
SWSYNC bit is cleared only at the boundary cycle, so the user does not know when this bit will be cleared.
Thus, it is possible a new write to set SWSYNC happens when FTM is clearing the SWSYNC because it
is the selected boundary cycle of PWM synchronization that was started previously by the software trigger
event.
Freescale Semiconductor
Note
All hardware trigger (input signals: trigger_0, trigger_1 and trigger_2) have this same behavior
synchronized trigger_0
PWM synchronization
write 1 to TRIG0 bit
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
by system clock
trigger_0 input
trigger 0 event
system clock
TRIG0 bit
Figure 11-62. Hardware trigger event
FlexTimer Module (FTMV1)
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