mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 307

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

(regardless of the SR[I] field) and each time the SR[I] mask changes from seven to a lower value while the
encoded request level remains at seven.
13.5
The reset state of the CF1_INTC module enables the default IRQ mappings and clears any software-forced
interrupt requests (INTC_FRC is cleared). On the first revision of silicon for this device, the wakeup
control register (INTC_WCR) is disabled, so it must be written before the processor executes any stop
instructions to properly exit from any wait or stop mode.Immediately after reset, the CF1_INTC begins its
cycle-by-cycle evaluation of any asserted interrupt requests and forms the appropriate encoded interrupt
level and vector information for the V1 Coldfire processor core. The ability to mask individual interrupt
requests using the interrupt controller’s IMR is always available, regardless of the level of a particular
interrupt request.
13.6
This section discusses three application topics: emulation of the HCS08’s one level interrupt nesting
structure, elevating the priority of two IRQs, and more details on the operation of the software interrupt
acknowledge (SWIACK) mechanism.
13.6.1
As noted in
masking is controlled by CCR[I], the interrupt mask flag: clearing CCR[I] enables interrupts, while setting
CCR[I] disables interrupts. The ColdFire architecture defines seven interrupt levels, controlled by the 3-bit
interrupt priority mask field in the status register, SR[I], and the hardware automatically supports nesting
of interrupts.
To emulate the HCS08’s 1-level IRQ capabilities on V1 ColdFire, only two SR[I] settings are used:
The ColdFire core treats the level seven requests as non-maskable, edge-sensitive interrupts.
ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers. This
allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level
contained in the status register as the first instruction in the ISR. In addition, the V1 instruction set
architecture (ISA_C) includes an instruction (STLDSR) that stores the current interrupt mask level and
loads a value into the SR. This instruction is specifically intended for use as the first instruction of an
interrupt service routine that services multiple interrupt requests with different interrupt levels. For more
details see the ColdFire Family Programmer’s Reference Manual. A MOVE-to-SR instruction also
performs a similar function.
To emulate the HCS08’s 1-level IRQ nesting mechanisms, the ColdFire implementation enables interrupts
by clearing SR[I] (typically when using RTE to return to a process) and disables interrupts upon entering
every interrupt service routine by one of three methods:
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1. Execution of STLDSR #0x2700 as the first instruction of an ISR.
Writing 0 to SR[I] enables interrupts.
Writing 7 to SR[I] disables interrupts.
Initialization Information
Application Information
Emulation of the HCS08’s 1-Level IRQ Handling
Table
13-1, the HCS08 architecture specifies a 1-level IRQ nesting capability. Interrupt
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Interrupt Controller (CF1_INTC)
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