mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 306

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Interrupt Controller (CF1_INTC)
13.4
The basic operation of the CF1_INTC is detailed in the preceding sections. This section describes special
rules applicable to non-maskable level seven interrupt requests and the module’s interfaces.
13.4.1
The CPU treats level seven interrupts as non-maskable, edge-sensitive requests, while levels one through
six are maskable, level-sensitive requests. As a result of this definition, level seven interrupt requests are
a special case. The edge-sensitive nature of these requests means the encoded 3-bit level input from the
CF1_INTC to the V1 ColdFire core must change state before the CPU detects an interrupt. A
non-maskable interrupt (NMI) is generated each time the encoded interrupt level changes to level seven
13-16
Functional Description
Handling of Non-Maskable Level 7 Interrupt Requests
MSCAN_wakeup
MSCAN_errors
IRQ Source
MSCAN_Rx
MSCAN_Tx
TPM3_ch0
TPM3_ch1
FTM2_ch5
FTM2_ovfl
TPM3_ovfl
force_lvl4
force_lvl3
force_lvl2
force_lvl1
SCI1_err
SCI2_err
SCI1_rx
SCI1_tx
SCI2_rx
SCI2_tx
ACMP1
ACMP2
ADC1
SPI1
KBI1
SPI2
IIC1
RTI
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 13-13. Interrupt Assignments
Level
4
4
4
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
Priority with
Level
mid
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Interrupt Source
INTC_FRC[lvl4]
INTC_FRC[lvl3]
INTC_FRC[lvl2]
INTC_FRC[lvl1]
Number
15
16
17
50
51
52
53
18
19
20
21
22
23
24
25
26
27
28
29
46
47
54
55
Freescale Semiconductor
Vector
106
114
115
116
117
107
108
110
111
118
119
109
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93