mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 110

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Parallel Input/Output Control
6.5.1.5
6.5.2
Port B is an 8-bit input/output port and also shares its pins with the TPM3 and the ADC peripherals. On
reset, the pins will default to the input state and under the I/O control. Enabling any of the shared peripheral
will take priority control over the pins. See
Port B is controlled by the registers listed below.
6-6
Reset:
PTASEn
PTADSn
Field
Field
7–0
7–0
W
R
PTB0 shares its pin with TPM3CH0 and AD1P0.
PTB1 shares its pin with TPM3CH1 and AD1P1.
PTB2 shares its pin with AD1P2.
PTB3 shares its pin with AD1P3.
PTB4 shares its pin with AD1P4.
PTB5 shares its pin with AD1P5.
PTB6 shares its pin with AD1P6.
PTB7 shares its pin with AD1P7.
PTADS7
Port B Registers
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
Port A Drive Strength Selection Register (PTADS)
0
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 6-6. Drive Strength Selection for Port A Register (PTADS)
PTADS6
0
6
Table 6-4. PTASE Register Field Descriptions
Table 6-5. PTADS Register Field Descriptions
PTADS5
0
5
Table 2-1
PTADS4
0
4
Description
Description
for details on pin function priorities.
PTADS3
3
0
PTADS2
0
2
PTADS1
Freescale Semiconductor
0
1
PTADS0
0
0

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