mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 39

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mcf51ac256a

Manufacturer Part Number
mcf51ac256a
Description
Mcf51ac Flexis
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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1
3.4
While the MCU is in secure mode, there are severe restrictions on which debug commands can be used.
In this mode, only the upper byte of the CPU’s XCSR, CSR2, and CSR3 registers can be accessed. See
Chapter 22, “Version 1 ColdFire Debug (CF1_DEBUG),”
3.5
Run mode is the normal operating mode for the MCF51AC256 series MCUs. This mode is selected when
the BKGD/MS pin is high at the rising edge of the internal reset signal. Upon exiting reset, the CPU fetches
the supervisor SP and PC from locations 0x(00)00_0000 and 0x(00)00_0004 in the memory map and
executes code starting at the newly set value of the PC.
3.6
Wait mode is entered by executing a STOP instruction after configuring the device as per
is, if the WAITE control bit is set when STOP is executed, the wait mode is entered. Upon execution of
the STOP instruction, the CPU enters a low-power state in which it is not clocked.
Freescale Semiconductor
Stop3 — Low voltage detections in
stop are disabled. If BDC is enabled,
stop4 will be invoked rather than
stop3.
Stop2 — Low voltage detections in
stop are disabled. If BDC is enabled,
stop4 will be invoked rather than
stop2.
ENBDM is located in the upper byte of the XCSR register which is write accessable only through BDC commands, see Debug
module
Mode of Operation
Section 22.3.3, “Configuration/Status Register 2 (CSR2).”
Secure Mode
Run Mode
Wait Mode
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Table 3-1. CPU / Power Mode Selections (continued)
STOPE WAITE ENBDM
1
1
SOPT
0
0
Register and Bit names
XCSR
0
0
1
LVDE LVDSE PPDC
for details.
0
0
x
x
SPMSC1
0
0
x
x
SPMS
C2
0
1
and bus clocks
MCG powered
off. LPO clock
MCG in stop
are off. LPO,
clock can be
RTI wakeup.
RTI wakeup.
mode. CPU
enabled for
enabled for
Peripheral
Reference
internal or
CPU and
external
Clocks
can be
Table
Modes of Operation
LVD disabled.
LVD disabled
LVD disabled
LVD disabled
Sub-System
in all modes
in stop only.
in stop only.
Affects on
Only RAM
Only RAM
powered.
powered.
3-1. That
3-3

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