mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 238

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

FlexTimer Module (FTMV1)
11.4.6
The edge-aligned mode is selected when:
The EPWM period is determined by (FTMxMODH:FTMxMODL - FTMxCNTINH:FTMxCNTINL +
0x0001) and the pulse width (duty cycle) is determined by (FTMxCnVH:FTMxCnVL -
FTMxCNTINH:FTMxCNTINL).
The TOF bit is set and the timer overflow interrupt is generated (if TOIE = 1) at the end of the EPWM
period (when the FTM counter changes from FTMxMODH:FTMxMODL to
FTMxCNTINH:FTMxCNTINL). The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE
= 1) at the end of the pulse width, that is, at the channel (n) match (when the FTM counter =
FTMxCnVH:FTMxCnVL).
This type of PWM signal is called edge-aligned because the leading edges of all PWM signals are aligned
with the beginning of the period, which is the same for all channels within an FTM.
EPWM mode can be used when other channels in the same FTM are configured for input capture, output
compare or combine modes.
If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the FTMxCnVH:FTMxCnVL registers
the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however the channel (n)
output is not controlled by FTM.
If (ELSnB:ELSnA = 1:0) then the channel (n) output is forced high at the counter overflow (when the
FTMxCNTINH:FTMxCNTINL register contents are loaded into the FTM counter), and it is forced low at
the channel (n) match (when the FTM counter = FTMxCnVH:FTMxCnVL)
11-38
•
(FTMEN = 0) and (COMBINE = 0) and (CPWMS = 0) and (MSnB = 1)
channel (n) output
Edge-aligned PWM (EPWM) mode
Output compare mode is only available when (FTMEN = 0) and
(FTMxCNTINH:FTMxCNTINL = 0x0000). Output compare mode with
(FTMEN = 1) or (FTMxCNTINH:FTMxCNTINL not = 0x0000) is not
recommended and its results are not guaranteed.
Figure 11-38. EPWM period and pulse width with ELSnB:ELSnA = 1:0
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
counter overflow
pulse
width
period
channel (n) match
counter overflow
NOTE
channel (n) match
counter overflow
(Figure
channel (n) match
Freescale Semiconductor
11-39).