mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 413

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

18.2.2
This read/write register controls various optional features of the SCI system.
Freescale Semiconductor
SCISWAI
SBR[7:0]
Reset
LOOPS
WAKE
RSRC
Field
Field
7–0
ILT
M
7
6
5
4
3
2
W
R
LOOPS
SCI Control Register 1 (SCIxC1)
Baud Rate Modulo Divisor. These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo
divide rate for the SCI baud rate generator. When BR is cleared, the SCI baud rate generator is disabled to
reduce supply current. When BR is 1 – 8191, the SCI baud rate equals BUSCLK/(16×BR). See also BR bits in
Table
Loop Mode Select. Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS is set,
the transmitter output is internally connected to the receiver input.
0 Normal operation — RxD and TxD use separate pins.
1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See
SCI Stops in Wait Mode
0 SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes up the CPU.
1 SCI clocks freeze while CPU is in wait mode.
Receiver Source Select. This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS is set,
the receiver input is internally connected to the TxD pin and RSRC determines whether this connection is also
connected to the transmitter output.
0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the SCI does not use the RxD
1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.
9-Bit or 8-Bit Mode Select
0 Normal — start + 8 data bits (lsb first) + stop.
1 Receiver and transmitter use 9-bit data characters
Receiver Wakeup Method Select. Refer to
0 Idle-line wakeup.
1 Address-mark wakeup.
Idle Line Type Select. Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do
not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to
Section 18.3.3.2.1, “Idle-Line
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
0
7
RSRC
pins.
start + 8 data bits (lsb first) + 9th data bit + stop.
18-1.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
bit.) RxD pin is not used by SCI.
SCISWAI
0
6
Figure 18-5. SCI Control Register 1 (SCIxC1)
Table 18-2. SCIxBDL Field Descriptions
Table 18-3. SCIxC1 Field Descriptions
RSRC
Wakeup” for more information.
0
5
Serial Communication Interface (SCI)Serial Communications Interface (SCIV4)
Section 18.3.3.2, “Receiver Wakeup
M
0
4
Description
Description
WAKE
3
0
ILT
0
2
Operation” for more information.
PE
0
1
PT
0
0
18-5