mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 161

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Chapter 8
Analog Comparator (ACMPV3)
8.1
This device includes two independent analog comparators (ACMPs), named ACMP1 and ACMP2.
The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages or for
comparing one analog input voltage to an internal reference voltage. The comparator circuit can operate
across the full range of the supply voltage (rail-to-rail operation).
8.1.1
When using the bandgap reference voltage for input to ACMP1+ and/or ACMP2+, the user must enable
the bandgap buffer by setting SPMSC1[BGBE] (see
and Control 1 Register
8.1.2
The ACMP modules can be configured to connect the output of the analog comparator to a TPM input
capture channel 0 by setting the corresponding ACIC1 bit in the SOPT2 register (see
“System Options 2 (SOPT2)
regardless of the configuration of the TPMx module.
The ACMP1 and ACMP2 outputs can be connected to FTM1CH0 and TPM3CH0, respectively.
In addition, the ACMP1 and ACMP2 outputs can be connected to FTM1 and FTM2, respectively, to be
used as a synchronization signal. See
for details.
8.1.3
The bus clock to both ACMP modules can be gated on and off using the SCGC2[ACMPx] bit (see
Section 5.9.11, “System Clock Gating Control 2 Register
enables the bus clock to this module. To conserve power, the SCGC2[ACMPx] bit can be cleared to disable
the clock to this module when not in use. See
Freescale Semiconductor
Introduction
ACMP Configuration Information
ACMP/FTM/TPM Configuration Information
ACMP Clock Gating
Ignore any references to stop1 low-power mode in this chapter, because this
device does not support it.
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
(SPMSC1)”). See data sheet for the value of the bandgap voltage.
Register. With ACIC1 set, the TPMxCH0 pin is not available externally
Section 11.3.11, “FTM Synchronization Register
Section 5.8, “Peripheral Clock
NOTE
Section 5.9.7, “System Power Management Status
(SCGC2)”). This bit is set after any reset, which
Gating,” for details.
Section 5.9.9,
(FTMxSYNC)”,
8-1