mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 470

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

16-Bit Serial Peripheral Interface (SPI16)
20-30
SPIxC1=0x54(%01010100)
SPIxC2 = 0xC0(%11000000)
SPIxBR = 0x00(%00000000)
SPIxS = 0x00(%00000000)
SPIxMH = 0xXX
SPIxML = 0xXX
SPIxDH = 0xxx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6:4
Bit 3:0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:0
In 16-bit mode, this register holds bits 8–15 of the hardware match buffer. In 8-bit mode, writes to this register will be
ignored.
Holds bits 0–7 of the hardware match buffer.
In 16-bit mode, this register holds bits 8–15 of the data to be transmitted by the transmit buffer and received by the
receive buffer.
SPIE
SPE
SPTIE
MSTR
CPOL
CPHA
SSOE
LSBFE
SPMIE
SPIMODE
MODFEN
BIDIROE
SPISWAI
SPC0
SPRF
SPMF
SPTEF
MODF
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 0
= 1
= 1
= 0
= 0
= 0
= 0
= 0
= 0
= 0
= 000
= 0000
= 0
= 0
= 0
= 0
= 0
Disables receive and mode fault interrupts
Enables the SPI system
Disables SPI transmit interrupts
Sets the SPI module as a master SPI device
Configures SPI clock as active-high
First edge on SPSCK at start of first data transfer cycle
Determines SS pin function when mode fault enabled
SPI serial data transfers start with most significant bit
SPI hardware match interrupt enabled
Configures SPI for 16-bit mode
Unimplemented
Disables mode fault function
SPI data I/O pin acts as input
Unimplemented
SPI clocks operate in wait mode
uses separate pins for data input and output
Unimplemented
Sets prescale divisor to 1
Sets baud rate divisor to 2
Flag is set when receive data buffer is full
Flag is set when SPIMH/L = receive data buffer
Flag is set when transmit data buffer is empty
Mode fault flag for master mode
Unimplemented
Freescale Semiconductor