mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 490

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

Timer/PWM Module (TPMV3)
The channel match value in the TPM channel registers (times two) determines the pulse width (duty cycle)
of the CPWM signal
clears the CPWM output signal and a channel match occurring while counting down sets the output. The
counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then counts down
until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin
transitions are lined up at the same system clock edge. This type of PWM is also required for some types
of motor drives.
Input capture, output compare, and edge-aligned PWM functions do not make sense when the counter is
operating in up/down counting mode so this implies that all active channels within a TPM must be used in
CPWM mode when CPWMS is set.
The timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected PWM
pulse widths. Writes to any of the registers TPMxCnVH and TPMxCnVL actually write to buffer registers.
In center-aligned PWM mode, the TPMxCnVH:TPMxCnVL registers are updated with the value of their
write buffer according to the value of CLKSB:CLKSA bits:
When TPMxCNTH:TPMxCNTL equals TPMxMODH:TPMxMODL, the TPM can optionally generate a
TOF interrupt (at the end of this count).
21.5
21.5.1
The TPM is reset whenever any MCU reset occurs.
21-18
•
•
If CLKSB and CLKSA are cleared, the registers are updated when the second byte is written
If CLKSB and CLKSA are not cleared, the registers are updated after both bytes were written, and
the TPM counter changes from (TPMxMODH:TPMxMODL – 1) to
(TPMxMODH:TPMxMODL). If the TPM counter is a free-running counter, the update is made
when the TPM counter changes from 0xFFFE to 0xFFFF.
Reset Overview
General
TPMxMODH:TPMxMODL
TPMxCHn
TPM counter =
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
(Figure
Figure 21-15. CPWM period and pulse width (ELSnA=0)
21-15). If ELSnA is cleared, a channel match occurring while counting up
channel match
(count down)
2 × TPMxMODH:TPMxMODL
2 × TPMxCnVH:TPMxCnVL
TPM counter = 0
pulse width
period
channel match
(count up)
TPMxMODH:TPMxMODL
TPM counter =
Freescale Semiconductor