mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 495

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

There are two fields in debug registers which provide revision information: the hardware revision level in
CSR and the 1-pin debug hardware revision level in CSR2.
revisions.
22.1.2
The Version 1 ColdFire debug definition supports the following features:
Freescale Semiconductor
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•
•
•
•
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with VBus
Revision
CF1_B+
CF1_B+
B+
concurrent operation of the processor and BDM-initiated memory commands. In addition, the
option is provided to allow interrupts to occur. See
Program trace support—The ability to determine the dynamic execution path through an
application is fundamental for debugging. The V1 solution implements a trace buffer that records
processor execution status and data, which can be subsequently accessed by the external emulator
system to provide program (and optional partial data) trace information. See
Support With the Visibility Bus Disabled (CSR[VBD] =
Additionally, this device includes the VBus interface signals which support real-time program
trace by outputting the processor execution status and debug data to an external emulator system.
See
A
B
Classic ColdFire DEBUG_B+ functionality mapped into the single-pin BDM interface
Real time debug support, with 6 hardware breakpoints (4 PC, 1 address pair and 1 data) that can be
configured into a 1- or 2-level trigger with a programmable response (processor halt or interrupt)
Capture of compressed processor status and debug data into on-chip trace buffer provides program
(and optional slave bus data) trace capabilities
On-chip trace buffer provides programmable start/stop recording conditions plus support for
obtrusive or PC-profiling modes
Debug resources are accessible via single-pin BDM interface or the privileged WDEBUG
instruction from the core
Support for real-time program (and optional partial data) trace using the visibility bus
Section 22.4.3, “Real-Time Trace Support with the Visibility Bus Enabled (CSR[VBD] =
Features
CSR[HRL]
0000
0001
1001
1001
1001
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
CSR2[D1HRL]
0001
1001
N/A
N/A
N/A
Table 22-1. Debug Revision Summary
Initial ColdFire debug definition
BDM command execution does not affect hardware breakpoint logic
Added BDM address attribute register (BAAR)
BKPT configurable interrupt (CSR[BKD])
Level 1 and level 2 triggers on OR condition, in addition to AND
SYNC_PC command to display the processor’s current PC
Added 3 PC breakpoint registers PBR1–3
Converted to HCS08 1-pin BDM serial interface
Added PST compression and on-chip PST/DDATA buffer for program trace
CF1 debug plus visibility bus support
Section 22.4.2, “Real-Time Debug
Table 22-1
Enhancements
1)”.
summarizes the various debug
Version 1 ColdFire Debug (CF1_DEBUG)
Section 22.4.4, “Trace
Support”.
0]”.
22-3