mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 214

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

FlexTimer Module (FTMV1)
11.3.7
These read/write registers contain the captured FTM counter value of the input capture function or the
match value for the output modes. The channel registers are cleared by reset.
In input capture mode, reading either byte (FTMxCnVH or FTMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other half is read. This latching mechanism also resets
(becomes unlatched) when the FTMxCnSC register is written (whether BDM mode is active or not). Any
write to the channel registers will be ignored during the input capture mode.
When BDM is active, the read coherency mechanism is frozen such that the buffer latches remain in the
state they were in when the BDM became active, even if one or both halves of the channel value register
are read while BDM is active. This assures that if the user was in the middle of reading a 16-bit register
when BDM became active, it will read the appropriate value from the other half of the 16-bit value after
returning to normal execution. Any read of the FTMxCnVH and FTMxCnVL registers in BDM mode
bypasses the buffer latches and returns the value of these registers and not the value of their read buffer.
In output modes, writing to either byte (FTMxCnVH or FTMxCnVL) latches the value into a buffer. The
registers are updated with the value of their write buffer according to
registers with write
11-14
Reset
Reset
W
W
R
R
COMBINE
Bit 15
Bit 7
1
FTM Channel Value Registers (FTMxCnVH:FTMxCnVL)
0
0
7
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
CPWMS
buffers.”
0
Figure 11-8. FTM Channel Value Register High (FTMxCnVH)
Figure 11-9. FTM Channel Value Register Low (FTMxCnVL)
14
0
6
0
Table 11-7. Mode, Edge, and Level Selection (continued)
6
6
MSnB:MSnA
XX
13
5
0
5
5
0
ELSnB:ELSnA
12
0
4
0
4
4
X1
10
11
0
3
0
3
3
Combine PWM
Mode
Section 11.4.10, “Load of the
10
0
2
0
2
2
High-true pulses (set on
channel (n) match, and
clear on channel (n+1)
Low-true pulses (clear
on channel (n) match,
and set on channel
Configuration
(n+1) match)
Freescale Semiconductor
match)
1
9
0
1
1
0
Bit 8
Bit 0
0
0
0
0