mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 438

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

8-Bit Serial Peripheral Interface (SPIV3)
pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT
waveform applies to the slave select output from a master (provided MODFEN and SSOE are set). The
master SS output asserts one-half SPSCK cycle before the start of the transfer and negates at the end of the
eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.
When CPHA is set, the slave begins to drive its MISO output when SS asserts, but the data is not defined
until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI
output of the master and the MISO output of the slave. The next SPSCK edge causes the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge,
the SPI shifter shifts one bit position that shifts in the bit value that was sampled, and shifts the second data
bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave,
respectively. When CHPA is set, the slave’s SS input is not required to negate between transfers.
Figure 19-10
are shown for reference with bit 1 starting as the slave is selected (SS IN asserts), and bit 8 ends at the last
SPSCK edge. The msb first and lsb first lines show the order of SPI data bits depending on the setting of
SPI1C1[LSBFE]. Both variations of SPSCK polarity are shown, but only one of these waveforms applies
for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI
input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from
19-12
(MISO OR MOSI)
(MASTER OUT)
(REFERENCE)
(SLAVE OUT)
SAMPLE IN
(CPOL = 0)
(CPOL = 1)
msb FIRST
(MASTER)
Bit Time #
lsb FIRST
(SLAVE)
SS OUT
SPSCK
SPSCK
MOSI
MISO
SS IN
shows the clock formats when CPHA is cleared. At the top of the figure, the eight bit times
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 19-9. SPI Clock Formats (CPHA = 1)
BIT 7
BIT 0
1
BIT 6
BIT 1
2
...
...
...
BIT 2
BIT 5
6
BIT 1
BIT 6
7
Freescale Semiconductor
BIT 0
BIT 7
8