mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 377

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

16.3.5
Freescale Semiconductor
OSCINIT
FTRIM
LOLIE
Field
Field
PLLS
CME
1
0
7
6
5
Reset:
W
R
MCG Control Register 3 (MCGC3)
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE,
PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the crystal
oscillator clock have completed. This bit is only cleared when either EREFS is cleared or when the MCG is in
either FEI, FBI, or BLPI mode and ERCLKEN is cleared.
MCG Fine Trim — Controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM will
increase the period and clearing FTRIM will decrease the period by the smallest amount possible.
If an FTRIM value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value from
the nonvolatile memory location to this register’s FTRIM bit.
Loss of Lock Interrupt Enable — Determines if an interrupt request is made following a loss of lock indication.
The LOLIE bit only has an effect when LOLS is set.
0 No request on loss of lock.
1 Generate an interrupt request on loss of lock.
PLL Select — Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all
modes. If the PLLS is set, the FLL is disabled in all modes.
1 PLL is selected
0 FLL is selected
Clock Monitor Enable — Determines if a reset request is made following a loss of external clock indication. The
CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external
clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2
register). Whenever the CME bit is set to a logic 1, the value of the RANGE bit in the MCGC2 register should not
be changed. If the external reference clock is set to be disabled when the MCG enters STOP mode
(EREFSTEN=0), then the CME bit should be set to a logic 0 before the MCG enters STOP mode. Otherwise a
reset request may occur while in STOP mode.
0 Clock monitor is disabled.
1 Generate a reset request on loss of external clock.
Table 16-6. MCG Status and Control Register Field Description (continued)
LOLIE
7
0
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
PLLS
Table 16-7. MCG PLL Register Field Descriptions
0
6
Figure 16-6. MCG PLL Register (MCGPLL)
CME
0
5
DIV32
0
4
Description
Description
0
3
Multipurpose Clock Generator (MCGV3)
0
2
VDIV
0
1
1
0
16-9