mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 135

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

To support dual stack pointers, the following two supervisor instructions are included in the ColdFire
instruction set architecture to load/store the USP:
These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other
instruction references to the stack pointer, explicit or implicit, access the active A7 register.
7.2.4
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. The extend bit (X) is also an input operand during multiprecision
arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare
(CMP), Bcc, or Scc instructions are executed.
Freescale Semiconductor
Reset:
BDM: LSB of Status Register (SR)
move.l Ay,USP;move to USP
move.l USP,Ax;move from USP
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
R
BDM: Load: 0x6F (A7)
Load: 0xEE (SR)
Store: 0xCE (SR)
W
R
Condition Code Register (CCR)
Store: 0x4F (A7)
Load: 0xE0 (OTHER_A7)
Store: 0xC0 (OTHER_A7)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
The USP must be initialized using the
entry into user mode.
The SSP is loaded during reset exception processing with the contents of
location 0x(00)00_0000.
7
0
0
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Figure 7-4. Stack Pointer Registers (A7 and OTHER_A7)
0
0
6
Figure 7-5. Condition Code Register (CCR)
0
0
5
NOTE
—
X
4
move.l Ay,USP
Address
—
N
3
OTHER_A7: Supervisor or BDM read/write
instruction before any
Access: A7: User or BDM read/write
—
Z
2
8
7
6
Access: User read/write
5
—
V
1
4
3
BDM read/write
2
ColdFire Core
1
—
C
0
0
7-5