mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 436

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

8-Bit Serial Peripheral Interface (SPIV3)
19.4.5
Reads of this register returns the data read from the receive data buffer. Writes to this register write data
to the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer
initiates an SPI transfer.
Data should not be written to the transmit data buffer unless SPI1S[SPTEF] is set, indicating there is room
in the transmit buffer to queue a new transmit byte.
Data may be read from SPI1D any time after SPRF is set and before another transfer is finished. Failure
to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition
and the data from the new transfer is lost.
19-10
Reset
SPTEF
MODF
SPRF
Field
3–0
7
6
5
4
W
R
SPI Data Register (SPI1D)
SPI Read Buffer Full Flag. SPRF is set at the completion of an SPI transfer to indicate that received data may
be read from the SPI data register (SPI1D). SPRF is cleared by reading SPRF while it is set, then reading SPI1D.
0 No data available in the receive data buffer
1 Data available in the receive data buffer
Reserved, should be cleared.
SPI Transmit Buffer Empty Flag. This bit is set when there is room in the transmit data buffer. It is cleared by
reading SPI1S with SPTEF set, followed by writing a data value to the transmit buffer at SPI1D. SPI1S must be
read with SPTEF set before writing data to SPI1D or the SPI1D write is ignored. SPTEF generates a CPU
interrupt request if SPI1C1[SPTIE] is also set. SPTEF is automatically set when a data byte transfers from the
transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift register
and no transfer in progress), data written to SPI1D is transferred to the shifter almost immediately so SPTEF is
set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After completion
of the transfer of the value in the shift register, the queued value from the transmit buffer is automatically moved
to the shifter and SPTEF is set, indicating there is room for new data in the transmit buffer. If no new data is
waiting in the transmit buffer, SPTEF remains set and no data moves from the buffer to the shifter.
0 SPI transmit buffer not empty
1 SPI transmit buffer empty
Master Mode Fault Flag. MODF is set if the SPI is configured as a master and the slave select input asserts,
indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only
when MSTR and MODFEN are set and SSOE is cleared. Otherwise, MODF is never set. MODF is cleared by
reading MODF while it is 1, then writing to the SPI1C1 register.
0 No mode fault error
1 Mode fault error detected
Reserved, should be cleared.
0
7
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
0
6
Table 19-5. SPI1S Register Field Descriptions
Figure 19-8. SPI Data Register (SPI1D)
0
5
0
4
Description
Data
3
0
0
2
Freescale Semiconductor
0
1
0
0