mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 212

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

FlexTimer Module (FTMV1)
It is recommended to initialize the FTM counter (write to FTMxCNTH or FTMxCNTL) before writing to
the FTM modulo registers to avoid confusion about when the first counter overflow will occur.
11.3.6
FTMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt
enable, channel configuration, and pin function.
11-12
Reset
Reset
CHnIE
CHnF
MSnB
Field
W
W
7
6
5
R
R
CHnF
Bit 7
Channel (n) flag. When channel (n) is an input-capture channel, this read/write bit is set when an active edge
occurs on the channel (n) pin. When channel (n) is an output compare or edge-aligned PWM channel, CHnF is
set when the value in the FTM counter matches the value in the FTM channel (n) value registers. When channel
(n) is center-aligned PWM channel, CHnF is set twice during each CPWM cycle (one at the start and another at
the end of the active duty cycle period) when the value in the FTM counter matches the value in the FTM channel
(n) value registers. When channel (n) is an edge-aligned/center-aligned PWM channel and the duty cycle is set
to 0% or 100%, CHnF will not be set even when the value in the FTM counter registers matches the value in the
FTM channel (n) value registers. When channel (n) is in combine mode, CHnF is always set when the value in the
FTM counter matches the value in the FTM channel.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by
reading FTMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs
before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence
is completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a
previous CHnF.
Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect.
0 No input capture or match event occurred on channel (n)
1 Input capture or match event on channel (n)
Channel (n) interrupt enable. This read/write bit enables interrupts from channel (n). Reset clears CHnIE.
0 Channel (n) interrupt requests disabled (use software polling).
1 Channel (n) interrupt requests enabled.
Mode select B for FTM channel (n). Refer to the summary of channel mode and setup controls in
MSnB bit is write protected, this bit can only be written if WPDIS = 1.
FTM Channel (n) Status and Control Register (FTMxCnSC)
0
0
0
7
7
Figure 11-7. FTM Channel (n) Status and Control Register (FTMxCnSC)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
= Unimplemented or Reserved
CHnIE
6
0
0
6
6
Table 11-6. FTMxCnSC Field Descriptions
MSnB
5
5
0
5
0
MSnA
4
0
0
4
4
Description
ELSnB
3
0
0
3
3
ELSnA
2
0
0
2
2
Freescale Semiconductor
1
1
0
1
0
0
Table
Bit 0
0
0
0
0
0
11-7.