mcf51ac256a Freescale Semiconductor, Inc, mcf51ac256a Datasheet - Page 551

• Manufacturer Part Number: mcf51ac256a
• Description: Mcf51ac Flexis
• Manufacturer: Freescale Semiconductor, Inc

22.4.3.1
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed
on DDATA depending on the CSR settings. CSR[BTB] also controls the number of address bytes
displayed, which is indicated by the PST marker value immediately preceding the DDATA nibble in the
PSTB that begins the data output.
Multiple byte DDATA values are displayed in least-to-most-significant order. The processor captures only
those target addresses associated with taken branches that use a variant addressing mode (RTE and RTS
instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and
all exception vectors).
The simplest example of a branch instruction using a variant address is the compiled code for a C language
case statement. Typically, the evaluation of this statement uses the variable of an expression as an index
into a table of offsets, where each offset points to a unique case within the structure. For such
Freescale Semiconductor
PST[3:0]
0x8–
0xB
0xC
0xD
0xE
0xF
0x4
0x5
0x6
0x7
Table 22-26. CF1 Debug Processor Status Encodings with VBus Enabled (continued)
Normal exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
Emulator mode exception processing. Displayed during emulation mode (debug interrupt or optionally
Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF until
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to
the DDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is
signaled on the PST port, followed by the appropriate marker, and then the data transfer on the DDATA port.
Transfer length depends on the WDDATA operand size.
Begin execution of taken branch or SYNC_PC command issued. For some opcodes, a branch target
address may be displayed on DDATA depending on the CSR settings. CSR[BTB] also controls the number
of address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins the
data output. See
SYNC_PC command has been issued.
Reserved
Begin execution of return from exception (RTE) instruction.
Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles. The value is
driven onto the PST port one PSTCLK cycle before the data is displayed.
0x8 Begin 1-byte transfer on DDATA
0x9 Begin 2-byte transfer on DDATA
0xA Begin 3-byte transfer on DDATA
0xB Begin 4-byte transfer on DDATA
generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle
mode, PST outputs are driven with 0xC until exception processing completes.
trace). Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until
exception processing completes.
Processor is stopped. Appears in multiple-cycle format when the processor executes a STOP instruction.
The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the
stopped mode is exited.
the processor is restarted or reset. See
Begin Execution of Taken Branch (PST = 0x5)
MCF51AC256 ColdFire Integrated Microcontroller Reference Manual, Rev. 5
Section 22.4.3.1, “Begin Execution of Taken Branch (PST =
Section 22.4.1.1, “CPU
Definition
Halt”.
Version 1 ColdFire Debug (CF1_DEBUG)
0x5)”. Also indicates that the
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